1. Field of the Invention
This invention relates to P-N junction isolation grids for semiconductor devices and method for making the same.
2. Description of the Prior Art
W. G. Pfann describes in "Zone Melting", John Wiley and Sons, Inc., New York (1966), a traveling solvent method to produce a P-N junction within the bulk of a semiconductor. In this method, either sheets or wires of a suitable metallic liquid are moved through a solid semiconductor material by employing a thermal gradient. Doped liquid-epitaxial material is left behind as the liquid wire migration progresses. Pfann also describes his thermal gradient zone melting process and desirable results obtained therefrom in his U.S. Pat. Nos. 2,739,088 and 2,813,048. Until recently, this process of temperature gradient zone melting has been practiced in an attempt to make a variety of semiconductor devices.
In U.S. Pat. No. 3,904,442, issued to Anthony and Cline, two of the inventors of this improved thermal gradient zone melting process, and in their copending application U.S. Ser. No. 519,913, filed on Nov. 1, 1974, there are described novel processing techniques which enable the teachings of W. G. Pfann to be commercially feasible. The improvements taught by Anthony and Cline enabled one to divide a wafer of semiconductor material into a plurality of electrically isolated regions in which electrical devices are manufactured. Further processing results in individual devices when the wafers are "diced" or divided into individual devices.
For example, with reference to FIG. 1, the geometric configuration 10 is produced in a wafer 12 of single crystal semiconductor material by a thermal gradient zone melting process taught by Anthony and Cline. Two or three sequential thermal gradient zone melting processings are required to produce the desired configuration 10. This is accomplished by using preferred wire directions and a (111) planar orientation for the major surface of the wafer of material. The result is three groups of spaced planar regions 14, 16 and 18 of a conductivity type which is opposite to that conductivity type of the wafer 12. P-N junctions 20, 22 and 24 are formed by the abutting surfaces of the material of opposite type conductivity of the body or wafers 12 and the respective planar regions 14, 16 and 18. The planar regions 14, 16 and 18 are oriented at a predetermined angle with respect to each other in order that after migration a first group of hexagonal shape regions 26 and a second group of triangular regions 28 are produced. The regions 26 and 28 are electrically isolated from each other and from mutually adjacent respective regions 26 or 28 by the regions 14, 16 and 18. The regions 28, however, represent a loss of semiconductor material since they are waste when the wafer 12 is separated into individual devices or chips, the functional semiconductor element being fabricated in the region 26.
The regions 28 result from two factors in commercial processing of the wafer or body 12. First, the regions 14, 16 and 18 cannot presently be formed simultaneously by the thermal gradient zone melting process. One must form each region 14, 16 and 18 individually or may form two simultaneously and then form the third region. Therefore, one must rely on at least two, and possibly three, sequences or processing. The reason is explained heretofore in the aforementioned references to Anthony and Cline's patent and patent application. Should one heretofore try to simultaneously migrate three metal wires to form the regions 14, 16 and 18, surface tension, more often than not, causes the metal to "ball up" upon initiation of the formation of the melt to be migrated.
Upon application of heat, the metal melts and begins to alloy with the semiconductor material at the beginning of the migration process. The balling up causes discontinuities in the planar regions 14, 16 and 18, primarily at the intersection thereof, and groups of regions 26 and 28 are not electrically isolated from each other at the end of the process. Therefore, after dicing the wafer into individual electrical devices manufactured in the regions 26 one or more of the separated devices may fail since the portion of the regions 14, 16 and 18 associated therewith, as well as the portion of the corresponding P-N junctions 20, 22, and 24 are relied upon to protect the electrical characteristics of the devices. Additionally, the alignment of masks became a problem also since careless handling and poor alignment of the same during processing may cause loss of product. Therefore, the orientation of the regions as shown, although producing waste semiconductor material, is still desirable in order to try to obtain as high yield of product as possible.
It is therefore an object of this invention to provide a new and improved method of practicing thermal gradient zone melting for producing electrical isolation grids which overcomes the deficiencies of the prior art.
Another object of this invention is to provide a new and improved method for simultaneously migrating three intersecting metal wires as a molten zone of metal-rich semiconductor material through a solid body of the same semiconductor material.
A further object of this invention is to provide an improved thermal gradient zone melting process which maximizes the effective use of the volume of material of a semiconductor wafer.
Other objects of this invention will, in part, be obvious and will, in part, appear hereafter.